Quizzes¶

Quiz 1¶

1. Represent the decimal number 75 as a 7-bit binary number: ( 1 ), and as a BCD code: ( 2 ). Then add an even parity bit at the most significant bit (MSB) of the BCD code to form a 9-bit code: ( 3 ).

2. Simplify the Boolean expression \(XY + \bar{X}Z + X\bar{Y} + \bar{Y}Z\) to its minimum number of literals:

   • A: \(Y + Z\)
   • B: \(X + Z\)
   • C: \(X + Y\)
   • D: \(X + Y + Z\)

3. Which of the following expressions has its dual equal to its complement?

   • A: \(\bar{A} + BC\)
   • B: \(\bar{A}B + BC\)
   • C: \(\bar{A}\bar{B} + BC\)
   • D: \(\bar{A}B + A\bar{B}\)

4. What is the sum-of-minterms (SOM) form of the expression \(F(A,B,C) = \bar{A}B + BC\)?

   • A: \(\sum m(2,3,7)\)
   • B: \(\sum m(0,1,4)\)
   • C: \(\sum m(2,4,6)\)
   • D: \(\sum m(2,3,6)\)

Quiz 2¶

1. For the function \(F = AB(C+D)+C(BD'+\bar{A}D)\), the literal cost is: ( 1 ), and the gate input cost with NOT (GN) is: ( 2 ).

2. Find the essential prime implicants for \(F(W,X,Y,Z)= \sum m(0,1,4,6,7,8,9,12,14,15)\):

   • A: \(Y'Z', XZ'\)
   • B: \(\bar{X}\bar{Y}, XY\)
   • C: \(XY, XZ'\)
   • D: \(Y'Z', \bar{X}\bar{Y}\)

3. Find a minimal sum-of-products (SOP) expression for the function \(F\) with the don’t-care conditions: \(F(A,B,C,D)=\sum m(1,5,6,13,14)+ \sum d(4,12)\):

   • A: \(B\bar{C}+\bar{A}\bar{C}D+BCD'\)
   • B: \(B\bar{D}+B\bar{C}+\bar{A}\bar{C}\)
   • C: \(\bar{C}D+B\bar{C}+B\bar{D}\)
   • D: \(B\bar{C}+B\bar{D}+\bar{A}\bar{C}D\)

4. How many implicants, prime implicants (PI), and essential prime implicants (EPI) are there in \(F(A,B,C)=\sum m(0,4,5)+ \sum d(1)\)?

   • A: 8, 1, 1
   • B: 7, 1, 1
   • C: 6, 1, 1
   • D: 5, 3, 1

Quiz 3¶

1. Find the \(t_\text{PHL}\) from input C to the output D, assuming \(t_\text{PHL}=0.20\text{ ns}\) and \(t_\text{PLH}=0.36\text{ ns}\) for each gate.

   

   • A: 0.56 ns
   • B: 0.6 ns
   • C: 0.76 ns
   • D: 0.92 ns

2. Consider a 4-input priority encoder with inputs \(D_3\), \(D_2\), \(D_1\), \(D_0\). The encoder responds to the most significant 1 (highest priority to \(D_3\)). It produces outputs \(A_1\), \(A_0\) and a valid flag \(V\), where \(V=1\) indicates at least one input is 1. What is the logic expression for \(V\)?

   • A: \(D_3D_2 + D_1D_0\)
   • B: \(D_3D_2 + D_1 + D_0\)
   • C: \(D_3D_2D_1 + D_0\)
   • D: \(D_3 + D_2 + D_1 + D_0\)

3. Please find the logic expression of output \(F\) in the figure.

   

   • A: $XY + X\bar{Y}$
   • B: $\bar{X}\bar{Y} + XY$
   • C: $\bar{X}Y + XY$
   • D: $\bar{X}Y + X\bar{Y}$

4. What specific Boolean function does the PLA implement for \(F_2\)?

   

   • A: $AC + BC$
   • B: $\bar{C}+\bar{A}\bar{B}$
   • C: $\bar{A}C + BC$
   • D: $AC + B$

Quiz 4¶

1. For the decimal number \((-32)_{10}\) represented as an 8-bit signed binary number:

   1. The signed-magnitude representation is ( 1 );
   2. The signed-1's complement representation is ( 2 );
   3. The signed-2's complement representation is ( 3 ).

2. Given two 4-bit signed 2's complement numbers, \(A=(0100)_2\) and \(B=(1101)_2\):

   1. The result of \(A-B\) is ( 1 );
   2. Does overflow occur?

3. Which of the following statements about latch and flip-flop behavior is CORRECT?

   • A: Metastable state in a latch occurs when both inputs (S and R) are held at logic 0, causing the outputs to oscillate indefinitely.
   • B: Oscillation in a basic SR latch happens when both inputs are 0 and then return to 1 simultaneously, leading to an undefined or endless switching state if gate delays are equal.
   • C: 1s catching is a problem in edge-triggered D flip-flops, where a brief glitch on the D input during the clock edge can cause an incorrect output.
   • D: A metastable state is a stable, long-term condition that can be intentionally used to store an intermediate logic value.

4. As the sequential circuit shown below, determine its input equation, output equation, and next state equation.

   

   • A: $D=X\oplus Y, Z=X+Y, Q(t+1)=D$
   • B: $D=X+Y, Z=X\oplus Y, Q=D(t+1)$
   • C: $D=X+Y, Z=X\oplus Y, Q(t+1)=D$
   • D: $D=X\oplus Y, Z=X+Y, Q=D(t+1)$

5. The timing parameters for the gates and flip-flops are as follows: NOT Gate: \(t_{pd}=0.75\text{ ns}\); XOR Gate: \(t_{pd}=3.0\text{ ns}\); AND Gate: \(t_{pd}=1.5\text{ ns}\); Flip-flop: \(t_{pd}=3.0\text{ ns}\), \(t_s=1.25\text{ ns}\), \(t_h=0.5\text{ ns}\). Find the longest path delay from positive clock edge to an external output, and the maximum frequency of operation of the circuit.

   

   • A: 7.75 ns, 130 MHz
   • B: 7.5 ns, 120 MHz
   • C: 4.75 ns, 180 MHz
   • D: 7.5 ns, 125 MHz

Quiz 5¶

1. What is the function of the following 4-bit counter with parallel load?

   

   • A: It counts from 0 to 12 and back to 0.
   • B: It counts from 0 to 9 and back to 0.
   • C: It counts from 0 to 10 and back to 0.

2. Given two 8-bit registers \(R1\) and \(R2\), with \(R1=(1011\ 0110)_2\) and \(R2=(0111\ 1010)_2\). After two microoperations:

   1. \(R1 \leftarrow sl\ R1\);
   2. \(R1 \leftarrow R1 \oplus R2\).

   Then \(R1=\) ( ? ). - A: \(0001\ 0110\) - B: \(0011\ 0110\) - C: \(1101\ 1110\) - D: \(0001\ 1110\)

3. In the sequential circuit shown below, if the initial value of the output \(Q_1Q_0\) is 00, what are the next four values of \(Q_1Q_0\)?

   

   • A: 11, 10, 01, 00
   • B: 10, 11, 01, 00
   • C: 10, 00, 01, 11
   • D: 11, 10, 00, 01

4. Choose the correct register transfer operations for the following diagram.

   

   • A: $t_1: R2 \leftarrow R1;\ t_3: R2 \leftarrow R0$
   • B: $t_1: R2 \leftarrow R1;\ t_1't_3: R2 \leftarrow R0$
   • C: $t_1t_3': R2 \leftarrow R1;\ t_3: R2 \leftarrow R0$

5. You are designing a synchronous sequential circuit to detect the sequence "101" on a serial input stream. What is the minimum number of states required for a Mealy-type circuit and a Moore-type circuit, respectively?

   • A: Mealy: 3 states; Moore: 3 states
   • B: Mealy: 4 states; Moore: 4 states
   • C: Mealy: 3 states; Moore: 4 states
   • D: Mealy: 4 states; Moore: 5 states

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